The present invention relates generally to digital counter circuits, and more particularly, to digital counter circuits which re-allocate counting operations in lower-order counters as a function of the number of events counted in order to improve counter life. The present invention also relates to counting methods for use with non-volatile counters which improve counter life.
In many conventional non-volatile counter applications, such as in digital odometer applications, and the like, the lower order counters are required to endure a great deal of stress. This stress is due to the fact that they must perform a non-volatile WRITE action on each count. This WRITE action requires that the counter change state during each WRITE cycle. Accordingly, this WRITE action stresses the counter bits that have changed state since the previous WRITE action. The bits that have not changed state since the previous WRITE action endure a non-stressful non-volatile WRITE action which reinforces the data.
Therefore, lower order bits receive the burden of the stress, since they must change state more often than higher order bits. In an odometer application, for example, this is easy to see. In an odometer, the units decade is stressed each count, while the tens decade is stressed each 10 counts, and so forth for all decades of the counter. Accordingly, counter wear-out results from the multiple non-volatile writing of opposite data in any one bit of the counter.